开发板介绍

EGO1采用Xilinx Artix-7系列XC7A35T-1CSG324C FPGA，其搭载一个100MHz的时钟芯片，输出的时钟信号直接与FPGA全局时钟输入引脚（P17）相连。若设计中还需要其他频率的时钟，可以采用FPGA内部的MMCM生成。

通用I/O口方面，通用I/O接口外设包括2个专用按键、5个通用按键、8个拨码开关、1个8位DIP开关、16个LED灯、8个七段数码管。五个通用按键，默认为低电平，按键按下时输出高电平。

详细参数及引脚对照表可在用户手册中查阅

EGO1用户手册

本次使用的EGO1开发板芯片型号为：xc7a35tcsg324-1

代码部分

Sources代码

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module v_smg_1(
    input clk,
    input rst,
    input[15:0] sw, //开关
    output[7:0] seg,//段选，高有效
    output[7:0] seg1,
    output[7:0] an //位选，低有效
);
    reg[18:0] divclk_cnt = 0;//分频计数器
    reg divclk = 0;//分频后的时钟
    reg[7:0] seg=0;//段码
    reg[7:0] seg1=0;
    reg[7:0] an=8'b00000001;//位码
    reg[3:0] disp_dat=0;//要显示的数据
    reg[2:0] disp_bit=0;//要显示的位
    parameter maxcnt = 50000;// 周期：50000*2/100M
    always@(posedge clk)
    begin
        if(divclk_cnt==maxcnt)
        begin
            divclk=~divclk;
            divclk_cnt=0;
        end
        else
        begin
            divclk_cnt=divclk_cnt+1'b1;
        end
    end
    always@(posedge divclk) begin
        if(disp_bit >= 7)
            disp_bit=0;
         else
            disp_bit=disp_bit+1'b1;
         case (disp_bit)
            3'b000 :
            begin
                
                an=8'b00000001;//显示第一个数码管，高电平有效
                seg1 = 8'h00;  //空
            end
            3'b001 :
            begin
                
                an=8'b00000010;//显示第二个数码管，低电平有效
                seg1 = 8'b01100110;   //4
            end
            3'b010 :
            begin
                
                an=8'b00000100;//显示第三个数码管，低电平有效
                seg1 = 8'b11011010;   //2
            end
            3'b011 :
            begin
                
                an=8'b00001000;//显示第四个数码管，低电平有效
                seg1 = 8'b11111100;   //0
            end
            3'b100 :
            begin
                
                an=8'b00010000;//显示第五个数码管，低电平有效
                seg = 8'b11011010;    //2
            end
            3'b101 :
            begin
                
                an=8'b00100000;//显示第六个数码管，低电平有效
                seg = 8'b00011110;    //t
            end
            3'b110 :
            begin
                
                an=8'b01000000;//显示第七个数码管，低电平有效
                seg = 8'b00001100;    //I
            end
            3'b111 :
            begin
                
                an=8'b10000000;//显示第八个数码管，低电平有效
                seg = 8'b01101110;    //H
            end
            default:
            begin
                disp_dat=0;
                an=8'b00000000;
            end
        endcase
    end

endmodule

Constraints代码

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## clk
set_property PACKAGE_PIN P17 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
## switch
set_property PACKAGE_PIN P5 [get_ports {sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
set_property PACKAGE_PIN P4 [get_ports {sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
set_property PACKAGE_PIN P3 [get_ports {sw[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
set_property PACKAGE_PIN P2 [get_ports {sw[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
set_property PACKAGE_PIN R2 [get_ports {sw[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
set_property PACKAGE_PIN M4 [get_ports {sw[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
set_property PACKAGE_PIN N4 [get_ports {sw[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
set_property PACKAGE_PIN R1 [get_ports {sw[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
set_property PACKAGE_PIN U3 [get_ports {sw[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
set_property PACKAGE_PIN U2 [get_ports {sw[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
set_property PACKAGE_PIN V2 [get_ports {sw[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
set_property PACKAGE_PIN V5 [get_ports {sw[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
set_property PACKAGE_PIN V4 [get_ports {sw[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
set_property PACKAGE_PIN R3 [get_ports {sw[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
set_property PACKAGE_PIN T3 [get_ports {sw[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
set_property PACKAGE_PIN T5 [get_ports {sw[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]

##smg位码
set_property PACKAGE_PIN G2 [get_ports an[7]]
set_property IOSTANDARD LVCMOS33 [get_ports an[7]]
set_property PACKAGE_PIN C2 [get_ports an[6]]
set_property IOSTANDARD LVCMOS33 [get_ports an[6]]
set_property PACKAGE_PIN C1 [get_ports an[5]]
set_property IOSTANDARD LVCMOS33 [get_ports an[5]]
set_property PACKAGE_PIN H1 [get_ports an[4]]
set_property IOSTANDARD LVCMOS33 [get_ports an[4]]
set_property PACKAGE_PIN G1 [get_ports an[3]]
set_property IOSTANDARD LVCMOS33 [get_ports an[3]]
set_property PACKAGE_PIN F1 [get_ports an[2]]
set_property IOSTANDARD LVCMOS33 [get_ports an[2]]
set_property PACKAGE_PIN E1 [get_ports an[1]]
set_property IOSTANDARD LVCMOS33 [get_ports an[1]]
set_property PACKAGE_PIN G6 [get_ports an[0]]
set_property IOSTANDARD LVCMOS33 [get_ports an[0]]

## 段码
set_property PACKAGE_PIN B4 [get_ports {seg[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[7]}]
set_property PACKAGE_PIN A4 [get_ports {seg[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
set_property PACKAGE_PIN A3 [get_ports {seg[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
set_property PACKAGE_PIN B1 [get_ports {seg[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
set_property PACKAGE_PIN A1 [get_ports {seg[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
set_property PACKAGE_PIN B3 [get_ports {seg[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
set_property PACKAGE_PIN B2 [get_ports {seg[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
set_property PACKAGE_PIN D5 [get_ports {seg[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]

# 段码2
set_property PACKAGE_PIN D4 [get_ports {seg1[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg1[7]}]
set_property PACKAGE_PIN E3 [get_ports {seg1[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg1[6]}]
set_property PACKAGE_PIN D3 [get_ports {seg1[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg1[5]}]
set_property PACKAGE_PIN F4 [get_ports {seg1[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg1[4]}]
set_property PACKAGE_PIN F3 [get_ports {seg1[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg1[3]}]
set_property PACKAGE_PIN E2 [get_ports {seg1[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg1[2]}]
set_property PACKAGE_PIN D2 [get_ports {seg1[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg1[1]}]
set_property PACKAGE_PIN H2 [get_ports {seg1[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg1[0]}]

字符更换

只需要更换Sources代码中对应注释部分的八位二进制编码即可，也可使用十六进制数表示，二进制码与数码管对应关系如下：

八段数码管

其中八位二进制数每一位从左到右依次对应abcdefg(dp)，本代码中“1”为点亮。

例如“H”为 01101110

下面列举了一些常见数字字母的编码：

字符 BIN HEX
0 11111100 FC
1 01100000 50
2 11011010 DA
3 11110010 F2
4 01100110 66
5 10110110 B6
6 10111110 BE
7 11100000 E0
8 11111110 FE
9 11110110 F6
A 11101110 EE
B(b) 00111110 3E
C 10011100 9C
D(d) 01111010 7A
E 10011110 9E
F 10001110 8E
H 01101110 6E
J 01111000 78
L 00011100 1C
N(n) 00101010 2A
P 11001110 CE
R® 00001010 0A
T(t) 00011110 1E
U 01111100 7C
Y(y) 01110110 76
- 00000010 02